Himanshi Sonava on Instagram: "Follow @electronicscamp for more . . Vivado/Eda playground: RTL codes in verilog or system verilog. Yosis : synthesis Xscheme or LTSpice to design schematics, ngspice : generate the spice netlist OpenRoad : PNR from Floor planning, placement , CTS and Route KLayout : DRCs Netgen: LVS OpenTime : STA analysis."