IEEE

A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

Abstract: This paper presents a 1.25-GS/s 7-b single-channel successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a low input frequency SNDR/SFDR of 41.4/51 dB, ...
IEEE

A Low Voltage CMOS Current Comparator with Offset Compensation

Abstract: Analysis and design of an inverter-based current comparator consisting of 3 cascaded inverters is presented. Ideally, the comparator has almost zero input offset current when all inverters ...