While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

SAN MATEO, Calif. — In conjunction with Tera Systems Inc., LSI Logic Corp. has put together a methodology and tool flow that let customers know up-front if they are developing register-transfer-level ...

The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero ...