EDN

ARM extends SIMD within next processor instruction set

CAMBRIDGE, England — Processor licensor ARM Holdings plc has launched a single instruction multiple data (SIMD) extension to its architecture called Neon. Neon addresses signal and media processing ...
Design-Reuse

Development and use of an Instruction Set Simulator of 68000-compatible processor core

This paper presents an instruction set simulator of a 32-bit CPU and explains its use in embedded software development. Interaction of the ISS with transaction level model of a complex peripheral ...
EDN

Reconfigurable processor combines extensible core with SRAM-based FPGA

This system-chip features an embedded reconfigurable processor built by joining a configurable and extensible processor core and a SRAM-based embedded FPGA. The following article will be presented at ...
Design-Reuse

ARC introduces 16/32-bit instruction set architecture to reduce memory requirements by up to 30 per cent

ARC's configurable processor adds the ability to run both 16 and 32-bit instructions on a 32-bit architecture, allowing designers to reduce memory requirements by up to 30%, resulting in both lower ...
New Electronics

Cortus launches new processor cores, instruction set

Processor IP developer Cortus has launched new cores– the APS23 and 25 – based on its V2 instruction set. The V2 instruction set extends functionality by adding 24bit instructions to the existing 16 ...
Semiconductor Engineering

Dual Instruction-Set Architecture, Supporting A TTA And RISC-V Instruction Set Via a Lightweight Microcode Hardware Unit

A technical paper titled “Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode” was published by researchers at Tampere University. “Transport triggered architectures ...